Abstract

Passive integration technologies gain more and more interest for cellular applications due to the increasing demand for integration of functionality for cost, performance and size reasons[1-4]. One of the examples is the 6" PASSI4 process of NXP semiconductors[2]. This process consists of high ohmic Si substrates with high quality RF components such as metal-insulator-metal (MIM) capacitors and thick metal inductors. The process also includes a thick backside metal and through wafer interconnect (TWI) via holes for low inductive grounding. In addition, a high density decoupling capacitor and a resistor are available. The process results in an RF component (a sub-module) which is utilized in a stacked power amplifier (PA)/front end module (FEM) which also includes active control and RF power technologies[4]. One of the main difficulties with such a passive technology is the characterization and process control. In an active process, the performance of the circuits or sub circuits during pre-testing is closely related to the end product performance. However, the relation between the performance of the sub-modules and the performance of the final module is not straightforward at all. In this paper we will show how we have solved this issue for the process release of PASSI4.

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