Revisiting Response Compaction in Space for Full-Scan Circuits With Nonexhaustive Test Sets Using Concept of Sequence Characterization

Abstract

This paper revisits response compaction in space and reports results on simulation experiments on ISCAS 89 full-scan sequential benchmark circuits using nonexhaustive (deterministic compact and pseudorandom) test sets in the design of space-efficient support hardware in the context of built-in self-testing (BIST) of VLSI circuits. The techniques used herein take advantage of sequence characterization as utilized by the authors earlier in response data compaction in the case of ISCAS 85 combinational benchmark circuits using ATALANTA, FSIM, and COMPACTEST, to realize space compression of ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA, FSIM, and MinTest, under conditions of both stochastic independence and dependence of single and double line errors.