Revisiting Cache Resizing

Abstract

We present a novel framework to dynamically reconfigure on-chip memory resources according to the changing behavior of the executing applications. Our framework enables smooth scaling (i.e., resizing) of the on-chip caches targeting both performance and power efficiency. In contrast to previous approaches, the resizing decisions in our framework are not tainted by transient events (e.g., misses) that are due to downsizing avoiding swinging the cache size due to trial-and-error resizing decisions. This minimizes both execution time penalty induced by downsizing decisions as well as the effective cache size. In addition, an inherent property of our approach is that the actual invalidation of the cache blocks and the corresponding write-backs of the cache dirty blocks are asynchronous to resizing decisions, ensuring a smooth transition from one size to another. This makes it possible to apply our framework even on write-back caches--a major limitation in previous proposals. The proposed framework is simple to implement requiring minimal hardware overhead ( $$<$$ < 1 % of the target cache). Using cycle-accurate simulations and a wide range of applications, we evaluate our approach against previously proposed cache resizing schemes for various cache sizes and types. In all cases, our experimental findings show significant benefits across the board in both power and performance.