ECS an endeavor towards providing similar cache reliability behavior in different programs

Abstract

The reliability of embedded processors is one of the major concerns in safety-critical applications. Reliability, in particular, is expressed within the cache memories which are the largest element of processors, and consequently one of the most vulnerable components that can remarkably affect the reliability, especially in deep transistor scaling. Therefore, evaluating the cache vulnerability is crucial in the design of a reliable processor, especially for safety-critical applications.It has been shown that using the same cache size for different programs leads to non-identical vulnerability patterns/phases through them. According to the literature, most of the related research works have exploited identical cache sizes for different programs in their reliability evaluations, while the cache reliability strictly depends on the cache size and program behavior. State-of-the-art attempts to find an appropriate cache size for different programs require a huge and complex design space exploration.In this work, we have introduced a fast-obtaining criterion for determining the Effective Cache Size (ECS) for embedded processors which considers inherent programs' reliability and performance properties based on the memory footprints of programs. According to the results, using the ECS for the experimented programs in a processor with reconfigurable cache, the reliability would be increased up to 43× on average with acceptable performance degradations (21 % on average).