Abstract
The parasitic bipolar effect in fully-depleted (FD) silicon-on-insulator (SOI) transistors is revisited including impact ionization and band-to-band tunneling. We tested the transfer characteristic curves for different temperature and drain voltage, combined with TCAD simulation to analyze the dominant mechanism of parasitic bipolar transistor (PBT). In addition, the influence of gate length on PBT has also been analyzed. The current gain β of the PBT was measured at different temperatures and drain voltages. Back-gate biasing was demonstrated to efficiently suppress the bipolar amplification. TCAD simulations showed that the parasitic bipolar effect enhanced the leakage power in circuits. A strategy to counter its effect is proposed based on the power analysis of 6 T SRAM cell with back-gate modulation.
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