Review Paper- Design and Development of UART Protocol Using Verilog with UVM Testbench

Abstract

Verification of a complex VLSI design is a tedious process. Verification of Integrated Circuits using System Verilog lacks the reusability of the test bench of the environment UVM provides control over simulation behaviour in a ordered systematic way and will be executed sequentially to avoid race condition. System Verilog is a language same alike Verilog with its own constructs. UVM is a framework of System Verilog classes from where test benches will be built. This paper presents the Design of UART using Verilog and verifying using UVM. The verification done in this paper provides the complete working of UART which can be tested using UART device The verification done using UVM will reduce the overall time consumption done by the logic gates. Since the tests of sequences are kept apart from the original test bench hierarchy and the reusability of stimulus will reduce the overall execution time. Keywords: Transmitter, Receiver, Baud rate, Synchronous Communication, Asynchronous Communication, FSM.