Review of Offset and Noise Reduction Techniques for CMOS

Abstract

Input referred offset voltage, 1/f noise and thermal noise are amplifier properties that directly restrict the ability of discerning signals beyond a certain limit. The ever increasing spectrum of applications of integrated circuits and trends in the semiconductor market have pushed engineers to design circuits with successively lower voltage, less power consumption, higher dynamic range, accurate gain and wider bandwidth, preferably altogether. Amplifiers input errors are key properties, which have to be minimized, however with the least negative impact upon the other equally important properties. This paper reviews some the most relevant techniques applied to reducing input errors of CMOS amplifiers aiming at to provide a condensed set of information that can help designers at the starting point of a new design of a precision analog circuit. The focus in all cases that were selected to be studied in this review work was the reduction of offset and noise regardless of any commitment of the used technique with other characteristics of the amplifier and its impacts on figures of merit like NEF and PEF.