Abstract

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The Performance of VLSI circuit is limited by clock distribution network since it consumes more power. This paper reviews a number of clock distribution network and presents analysis of their effectiveness and limitations, especially on energy efficiency. In this paper we show that when current-mode (CM) clock distribution network is used, average power can be reduced by 62% in comparison to traditional voltage-mode (VM) clocks.

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