RETRACTED: FPGA-Based Motion Estimation Algorithm Optimization

Abstract

The new international video compression standards (HEVC) are referred to as video motion detection and efficient physical education video encoding. HEVC is determined by calculating the increasing complexity of video compression efficiency of the remarkable possible. Motion estimation is the most complicated arithmetic unit video encoder. Integer motion estimation and HEVC 70%, accounted for, and the video encoder's complexity calculates fractional motion estimation. High-Level Synthesis (HLS) tools algorithms have been successfully used in digital signal processing on FPGA. According to the actual requirements of the project, it is set as sports video management, target detection, video acquisition and target tracking. In order to adapt the smoothing time, the hardware configure ration consists of two parts: the intermediate results of the final optical flow vector and the optical flow calculating module generates the derivative calculation to adapt the smoothing time. Run built processor, software. FPGA chip, designed for directing data flow management and hardware components. Recommend using a first interpolation HEVC FPGA implementation scores and Vivado HLS motion estimation. The sports video target detection and tracking system designed in this paper analyzes the scene to be detected, further analyzes the moving target trajectory, and tracks the target according to the trajectory.