RETRACTED ARTICLE: TSV Aware 3D IC Partitioning with Area Optimization

Abstract

A paradigm shift has been witnessed in microelectronic industry in recent days with more and more research works focusing on transformation of Integrated Circuits from 2 to 3D. Heterogeneous systems in the same platform are implemented via stacking several planar chips vertically based on through-silicon-via (TSV) technology. To overcome the optimization issue of 3D IC design, the shuffled frog leaping algorithm has been implemented, and optimization of area and TSVs count is achieved. The moth flame optimization is preferred because of its capability of acquiring efficient solution from the fitness function. And the probability is also estimated finally to forecast the best score for area optimization. Here the layer’s temperature is optimized by balancing the area and TSVs count using Moth flame optimization algorithm where the fitness function and flame number is updated for each iteration to obtain the area with best score. Thus, the performance is analyzed with the existing work to prove its superiority and the similar dataset was utilized for the comparison to analyze the optimization of TSVs count. Thus, it was experimentally verified that our proposed method achieves effective optimization in terms of reducing the area TSVs count.