Retention Behavior Using SiN Spacers Charging on nMOSFETs for Future Nonvolatile Memory Application

Abstract

The gate-to-drain nonoverlapped implantation (NOI) n-type metal-oxide-silicon field effect transistor (nMOSFET) devices, in which silicon nitride spacer acts as electron charge-trapping, have been explored for future nonvolatile memory application. The threshold voltage (Vth) shifts of programming devices were measured as a function of baking time ranging from 25 to 250°C. There are two distinct states: the first initial state has a fast Vth shift rate while the the Vth shift rate of the second state is significantly alleviative. Based on the development of an empirical model for testing at various temperatures, the threshold voltage shift of the two states can be individually fitted by Arrhenius equation. The positive charge-assisted tunneling and direct tunneling attributed to tunnel oxide using low-pressure chemical vaporization deposition (LPCVD) and rapid thermal oxidation (RTO) methods, respectively, are responsible for the electron charge loss. The increased decay rate of charge loss occurs at elevated temperature due to thermal-enhanced charge emission. Besides, the anomalous Vth increasing which results from the RTO-enhanced diffusion of channel dopants toward the silicon/oxide interface was found by experiment results.