HV PMOSFET Vth (threshold voltage) shift caused by HEIP after HTOL

Abstract

After PLR(product level reliability) HTOL(high temperature operating lifetime) test of HV PMOSFET, Vth (threshold voltage) shift is observed to increase due to PMOSFET leakage current, which is caused by Hot Electron Induced Punch Through(HEIP). Generally, LCD display driver IC requires high voltage of more than 10V and adopts MTI(middle trench isolation) scheme which is deeply trenched to get isolation characteristics on the high voltage according to chip shrinkage. It was found that electron trapping at interface between sidewall oxide and nitride liner in middle trench isolation(MTI) induces channel shorting at the corner of transistor, thereby resulting in the leakage current. In this paper, we propose the optimized sidewall thickness and the effectiveness of additional annealing process which have strong resistance against hot electron induced punch through regarding that offset leakage current is increased after HTOL(high temperature operating lifetime) stressing test for devices prepared with MTI processing scheme and it might be improved by the optimization of sidewall oxide thickness. Therefore, the threshold voltage(Vth) shift is seriously reduced due to the increase of immunity on the hot electron induced punch-through(HEIP) according to the increase of the sidewall thickness and adding annealing process as the thermal oxide layer of high temperature.