Abstract
The ATLAS pixel detector is the innermost tracking detector of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. It has a total active area of 1.7 m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of silicon read out by approximately 80 million electronic channels, which will detect particle tracks and decay vertices with a very high precision. After more than 10 years of development and construction it is the first time ever the whole detector has been operated together. The paper will illustrate the detector performance and give first results from the combined ATLAS cosmics runs.
Highlights
Many ATLAS physics analyses require precise determination of vertices for pattern recognition near the collision point
An optical signal transmission is used for the communication between modules and off-detector readout electronics, 1ToT is measured in units of Bunch Crossings (BC), with 1 BC equal to 25 ns
Each of a total of nine readout crates houses one Single Board Computer (SBC) and one TTC Interface Module (TIM), which interfaces a TTC crate. This crate, organized into three partitions distributes TTC signals from the Central Trigger Processor (CTP) and collects BUSY signal from the ReadOut Drivers (RODs), which, being transmitted to the CTP, can stop global ATLAS data acquisition
Summary
Many ATLAS physics analyses require precise determination of vertices for pattern recognition near the collision point. A vertex resolution below 12 μm, high granularity and efficiency combined with low mass of the detector material are needed for that. The search for rare events drives proton-proton collisions to take place every 25 ns at the full LHC luminosity of 1034 cm−2s−1, which requires fast hit identification. Selection of interesting events with the latency of 3.2 μs requires local buffering in the readout electronics. Most important is the tolerance of the 500 kGy radiation dose expected over the lifetime period of about 10 years. The pixel detector, employing silicon pixel hybrid technology, has been designed to fulfill these demands [1], [2]
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