Abstract

In this paper, a resource efficient architecture design for the circular Hough transform based on Field Programmable Gate Array (FPGA) technology is presented. The circular Hough transform is implemented to detect iris boundary in a binary edge image. A novel modular design is proposed to reduce the required memory space by 93% compared to the direct implementation while maintaining a high detection rate over 92%. The parallel-pipelined implementation of the proposed architecture demonstrates a high speed processing capability that is suitable to support real-time iris recognition in resource constrained systems. Therefore, the proposed technology can be used in portable consumer devices such as mobile phones and tablets where iris recognition application is involved.

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