Reset‐in‐set: improving PCM write throughput by reducing the peak power of multi‐bit writes

Abstract

Phase change memory (PCM) is a promising candidate for the main memory of future computer systems due to its merits such as high capacity and low standby power. However, its poor write performance is a critical issue for it to be fully adopted as main memory devices. Owing to high write power consumption and high write latency, the PCM's write throughput is severely limited under chip power restriction. A write throughput improvement technique called reset-in-set is proposed, which enables the PCM to concurrently execute more write requests by reducing the peak power of multi-bit writes. The peak write power reduction is achieved by delaying short ‘0’ writes until the lowest power region of long ‘1’ writes. This technique decreases average write latency substantially and simulation results show that reset-in-set increases system performance by up to 44%, with negligible implementation overhead.