DRAM write-only-cache for improving lifetime of phase change memory

Abstract

Due to its high density and low standby power, phase change memory (PCM) has been considered to be a promising alternative of DRAM while DRAM faces its scaling limits and serious power consumption. However, PCM cells can only endurance a maximum of 107-108 write operations, making a PCM based system have a lifetime of only hundreds of days on average, it is even worse for some memory intensive applications as their lifetime is only several days. Thus it is important to reduce write operations in order to extend the lifetime of PCM. In this paper, we propose a novel hybrid memory architecture combining DRAM with PCM. In the proposed architecture, DRAM acts as a write-only-cache (WoC) which only stores dirty data evicted from last level cache (LLC). Our simulation shows that compared to PCM-only based main memory, the proposed architecture increases the lifetime by 205%, the improvement is also up to 45.4% compared to the PCM based main memory with a DRAM as the off-chip cache. At the same time, the read latency reduces by 30.9%, at a cost of only 5.3% power consumption, compared to the typical DRAM cache hybrid architecture.