Research on Thermal Resistance Test Method of Stacked Package Based on High-precision Controllable Thermal Test Chip

Abstract

With the emergence of three-dimensional integrated circuits, the integration of chips has been rapidly improved. The volume is significantly smaller and the power consumption is significantly reduced, but the thermal effect problem is becoming more and more prominent. In a high-density integrated module, multiple heat sources will enhance the thermal coupling effect and generate high heat flux density points, resulting in component performance degradation or even failure. Therefore, in order to promote the development of 3D chip integration technology, it is necessary to master more optimized pre-package thermal design methods, and high-precision package thermal simulation and thermal test verification technology has become a key technology that must be broken through in the field of integrated circuit thermal management optimization. In this paper, for the three-dimensional stacked packaging structure, the thermal test verification chip has been designed and fabricated. The high-precision thermal resistance test and thermal simulation analysis technology research will be carried out. Hot-spot electrical transient thermal test technology realizes high-precision multi-heat source stacked package thermal resistance test verification at the design stage. The multi-heat source stacked package structure consists of thermal test verification chips and memory chips. Then by importing the thermal resistance test structure function into Flotherm software, the finite element simulation model is fitted and calibrated, and a thermal simulation model equivalent to the actual product packaging structure is established. The evaluation of the heat dissipation scheme of the stacked package in the early stage of the design can be realized, which provides effective technical support for the optimization design of the package heat dissipation structure.