Research on the effect of gate etching depth on the performance of GaN-based HEMTs under medium source-drain etching

Abstract

In this work, we investigated the effect of different gate etch depths on the device performance of GaN-based HEMTs under medium source-drain etching (Eds = 8–10 nm). First, the source-drain integral etching technology is used to obtain GaN-based HEMT devices with different source-drain etching depths. According to the experimental data, the optimal source-drain etching depth is 8–10 nm, which not only reduces the ohmic contact resistance to a certain extent but also increases the saturation current and improves the transconductance. To further obtain higher threshold voltages and improve the performance of HEMTs, we explored the effect of gate etch depth on the device performance of HEMTs under medium source-drain etching. According to the experimental results, it is concluded that the optimal depth of gate etching is 8–10 nm under the medium source-drain etching depth. It has not only high threshold voltage and high transconductance but also high saturation current. Moreover, its threshold voltage (−1.9 ± 0.13V), transconductance (148.7 ± 2.5 mS/mm), and saturation current (524.5 ± 5.7 mA/mm) are all higher than those of conventional HEMTs. The results show that it has great potential in the field of power devices.