Research on Power Efficient Clock Distribution Schemes for Switching Converters

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Trends in VLSI technology represents bottleneck for the future high performance computing architectures as the ratio of the power pins to the total package pins keeps on increasing. A viable solution to this is bottleneck is to have final power consumption on-chip. Switched Capacitor DC-DC Converters are the most preferred for on-chip power conversion. However, as the number of power conversion modules increases and they get distributed across the chip area, clock distribution for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. This paper presents a power efficient signaling topology for driving the clocks to higher interconnect lengths.