Research on a high-speed programmable pattern generation method with deep storage

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Aiming at digital system testing, the paper proposed a high-speed programmable pattern generation method with deep storage based on FPGA+DDR3 SDRAM. Among them, DDR3 solves the storage problem of large-capacity programmable pattern data. For the discontinuity of DDR3 data outputing, the asynchronous FIFO is inserted as a buffer after DDR3, and the FIFO input and output speed difference is used to continuously uniformize the bursts of uneven pattern data output from DDR3. For the problem that the pattern data rate is limited by the FPGA logic resources, the parallel pattern data is serialized by the dedicated high-speed serial transceiver integrated by the FPGA. And the data rate is multiple of its original data rate. For the high-speed serial pattern data jitter attenuation problem of dynamic data rate switching, the paper uses the jitter attenuation technology to reduce the random jitter of the reference clock of high-speed serial pattern data after generating the 8-bit resolution variable reference clock through DDS+PLL from 5ps rms to 1ps rms. In the paper, the multi-channel data rate reaches up to 3.35 Gbps. The pattern data storage depth is 4 Gbits, and the random jitter of the pattern signal is less than 3 ps rms.