Abstract
In 3D-system packaging technologies, eutectic bonding is the key technology of multilayer chip stacking and vertical interconnection. Optimized from the aspects of the thickness of the electroplated metal layer, the pretreatment of the wafer surface removes the oxide layer, the mutual alignment between the wafers, the temperature of the wafer bonding, the uniformity of pressure and the deviation of the bonding process. Under the pretreatment conditions of plasma treatment and citric acid cleaning, no oxide layer was obtained on the metal surface. Cu/Sn bumps bonded under the condition of 0.135 Mpa, temperature of 280 °C, Sn thickness of 3–4 μm and a Cu-thickness of five micrometers. Bonded push crystal strength ≥18 kg/cm2, the average contact resistance of the bonding interface is about 3.35 mΩ, and the bonding yield is 100%. All performance indicators meet and exceed the industry standards.
Highlights
The three-dimensional integration technology based on through-silicon via (TSV) achieves homogeneous or heterogeneous three-dimensional integration by making vertical via, which can greatly reduce the size of the chip, while improving interconnection density and electrical performance [1,2]
The non-baking was to prevent the bonding surface from oxidizing during the oven baking process. This proves that the segmented citric acid cleaning was more effective in removing the oxide layer, and the IPA cleaning was followed by oven baking
GrTohuips p4raosvtehsethbaetstthperosecgemsse. nted citric acid cleaning was more effective in removing the oxide layer, andAtmheonIPgAthcelewanaifnegr-wlevaselfoblolonwdiendgbmy eotvheondbsawkiinthg.dSiiffnecreetnhtepoavreanmwetaesrsn,oGt raoruepdu3cwinagsatthmeoosppthimereiz, ed comit bwinasatliiokneloyf two acfaeur-sleevseelcobnodnadriyngoxpiadraatmioent,esros. iFt iwguarseb9etistear gnroatptho opfetrhfoerbmonbdaiknigngt.emThpeerreaftourree, wcuerve in cwhohoicshe Gthreouoppt4imasiztheedbbeostnpdrioncgespsa. rameters were reflected in the bonding process
Summary
The three-dimensional integration technology based on through-silicon via (TSV) achieves homogeneous or heterogeneous three-dimensional integration by making vertical via, which can greatly reduce the size of the chip, while improving interconnection density and electrical performance [1,2]. This technology has broad application prospects in network big data and memory manufacturing, as well as MEMS systems and has become the fourth-generation advanced packaging technology with the most development potential [3]. The reliability problem caused by the ultra-fine pitch microbump interconnection will become more severe [6]
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