Abstract
The technology of formation of LSI structures on GaAs epitaxial layers, formed on Si-substrates of large diameter, is developed, which makes it possible at least by an order of magnitude to reduce the production cost of crystals due to epitaxial growth of GaAs layers and the use of technological equipment of silicon technology. This technology also enables the useof heterostructures to increase the speed of the LSI. An analysis of complex structures of different architecture of IC/LSI on GaAs epitaxial layers, formed on Si-substrates, is carried out. The influence of the scattering processes of charge carriers on the potential fluctuations on the magnitude and profile of the mobility of electrons along the thickness of the epitaxial structure is investigated. When using epitaxial technology in structures, there are no isoconcentric impurities of oxygen and carbon, which are the factors of scattering of charge carriers, which makes it possible to achieve high values of mobility of charge carriers. It is shown that the use of epitaxial layers of gallium arsenide eliminates the effects of isoconcentration impurities of oxygen and carbon in gallium arsenide layers that increases their purity. A test element was implemented that allows non-destructive measurement of the mobility of charge carriers in the technological cycle of the formation of LSI structures. This allows us to realise the electrophysical diagnosis of the reliability of the LSI at the stage of crystal manufacturing
Highlights
The progress in the development of IC/LSI technologies on gallium arsenide (GaAs) was characterized by significantly worse success than provided previously [1,2,3]
This is due to the problems of obtaining reproducible, less-defective initial materials and structures on Schottky field transistors (ShFTs) of submicron size with a small dispersion of the output parameters over the substrate plane
Since 2010, the volume of commercial products based on gallium arsenide has increased by several times [4]
Summary
The progress in the development of IC/LSI technologies on GaAs was characterized by significantly worse success than provided previously [1,2,3]. Development of the technology for obtaining reproducible, less-defective epitaxial gallium-arsenide structures of ShFT and non-destructive methods of electrophysical test control of the conductivity and mobility of electrons in GaAs epitaxial structures remains relevant and allows improving significantly the characteristics of LSI in general. The aim of the work is to develop submicron technology for obtaining less-defective epitaxial gallium-arsenide structures on Schottky transistors on silicon substrates using test diagnostic control. This will increase the speed of the LSI and reduce their production costs. The following tasks were performed: – technology of forming and designing of complementary pairs of ShFTs on GaAs epitaxial layers is developed; – test elements (hallotrons) are developed for technological control of parameters (mobility of charge carriers) of ShFTs; – design technological analysis of complex structures of LSI circuits on GaAs epitaxial layers with the use of highspeed complementary ShFTs is carried out
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