Requirements for contamination control in the gigabit era

Abstract

The effect of contamination, especially particles and organic materials in cleanrooms, on future device manufacturing was estimated. The number of particles deposited on wafer surfaces was calculated based on particle size distribution in real cleanrooms and the reported data on particle deposition velocity. DRAM yield trend was then calculated taking only particles from the cleanroom environment into account. Killer particle size is assumed to be one-third of the feature size according to the SIA roadmap. In the Gigabit era, a class 0.1-0.01 level environment will be necessary even with a shortened TAT (turn around time). The lower limit of particle density in conventional cleanroom air was estimated to be class 0.1-1 Level by particle generation by people, suggesting the use of a mini-environment fab system to produce high-grade cleanliness. A mini-environment system is also preferable for eliminating other contaminants such as organic compounds. However, box material and additions must be reexamined from the viewpoint of organic contamination control because some organic materials generated from wafer box easily adsorb on silicon surfaces and change the surface conditions.