Abstract
Through silicon via (TSV) based 3D integrated circuits (ICs) have become a popular approach to revive Moore's law. However, the reliability of a TSV is an important issue, as a faulty TSV can result in the failure of the entire 3D IC. Most of TSV faults can be detected during the testing process, however, detecting TSV aging faults during the testing process is impossible. Certain mechanisms are required to be deployed to control the reliability of the chip in the presence of aging faults. In this paper we propose some solutions to repair the TSVs suffering from moderate types of delay fault without re-routing through a spare TSV while meeting the specified constraints of the design. Our experimental results indicate the efficiency of our proposed methods in reducing the adverse effects of an aged TSV in terms of delay reduction.
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