Reordering method of test set based on vector eigenvalues using critical area estimation

Abstract

With the continuous shrinkage of integrated circuit feature sizes, circuit design has become increasingly complex, leading to issues such as rising test complexity and inefficiency. A dynamic adjustment method of test vectors for effective transistor critical area coverage based on the internal structure of the circuit is proposed. The test quality of the test vector is measured in terms of the transistor feature size relative to the size of the circuit unit. First, this method comprehensively considers the problem of circuit complexity. The test eigenvalue of each test vector is comprehensively calculated based on the overall test results. Then, the test vectors are sorted from the highest to the lowest test quality. Furthermore, during the testing process, the order of the test vectors is dynamically adjusted according to the eigenvalues of the test vectors. This method can significantly reduce the test time for failed integrated circuits. Experiments using ISCAS 89 and ITC 99 circuits show that the test process after reordering reduces the test time by 37.98% and 36.15%, respectively. Therefore, the test efficiency of the chip is improved and the test cost is optimized.