Remote Scavenging Technology Using Ti/TiN Capping Layer Interposed in a Metal/High-k Gate Stack

Abstract

High permittivity materials have been required to replace traditional SiO2 to be gate dielectric to extend Moore's law. However, growth of a thin SiO2-like interfacial layer (IL) is almost unavoidable during the deposition or subsequent high temperature anneal. This limits the scaling benefits of incorporating high-k dielectrics into transistors. In this work, a promising approach, in which O-scavenging metal layer and a barrier layer preventing scavenging metal diffusing into high-k gate dielectric are used to engineer the thickness of the IL, is reported. Using a Ti scavenging layer and TiN barrier layer on HfO2 dielectric, the effective removal of interfacial layer (IL) and almost no Ti diffusing into HfO2, have been confirmed by high resolution transmission electron microscopy (HRTEM), and X-ray photoelectron spectroscopy (XPS).