Reliable High Density STT-MRAM Products INVITED

Abstract

Magneto resistive random-access memory (MRAM) holds the potential to be a universal memory with its non-volatility, high speed, robust endurance, and system power savings capability. In the semiconductor memory and storage space, MRAM is poised to deliver the performance of working memory with the persistence of storage. The pioneer generation of MRAM product dubbed Toggle MRAM was first launched in 2006 and was based on magnetic field switching. Driven by continuous demand for lower power and higher density, spin transfer torque MRAM (STT-MRAM) was introduced into the market. In its commercialization, standalone STT-MRAM product saw rapid evolution toward higher density in which the memory density quadrupled every 2 years between 2015-2019 [1]. The successful scaling of STT-MRAM product is attributed to a concerted effort in materials engineering and the use of advanced process technologies. Most recently in 2019-2020, we saw two momentous events in MRAM development: Everspin launched a milestone 1Gb product [2], and 3 major foundries and 2 other companies announced their STT-MRAM product offerings [1].In this talk, we will review the fundamental aspects of STT-MRAM with a focus on read and write distributions of MRAM arrays. In order to achieve reliable high density STT-MRAM products it is critical to understand the contributions to these distributions and minimize the variation across the array. For instance, minimizing array write error rate (WER) relies much upon reducing the population of extrinsic magnetic tunnel junction (MTJ) bits in an array. A method was developed to quantify the population of extrinsic bits by calculating the switching failure rate upon doing N repeat of read-write sequence, which we call soft fail count. Figure 1(a) shows example of soft fail improvement by combining MTJ film engineering and process improvement. The soft fail count improvement is seen from both the reduction of outlier bits and tightening of main bits population to reach below the desired requirement. Figure 1(b) shows the median soft fail count plotted against wafer radius from center to edge. Such plot further elucidated the distinct contribution from MTJ film and process changes implemented. Detailed analysis shows that the MTJ film improvement reduces the extrinsic population and improved the switching reliability on the die level, while the process improvement extends the die uniformity across the wafer. These approaches were found to be additive when combined.A low operating voltage coupled with reliable switching (measured as distributions) is critical to integrating MTJ bits on silicon. Figure 2 shows the plots of normalized array operating voltage (Vop) and its sigma corresponding to the MTJ film and process improvement shown in Figure 1. Initial MTJ film change from A to B improved the Vop by 14% and significantly reduced the sigma by a factor 2.6x. Switching from process A to B using the improved film B improved the Vop by a further 3.3% with a comparable sigma level to process A. Finally, combining MTJ film C with Process B produced slight improvement in Vop and further reduction in sigma by 20%. This observation corroborated the reduction in bit error soft fail count shown in Figure 1.The improvement in bit-to-bit distribution is critical to enable reliable high density STT-MRAM products. In the talk, we will discuss the impact of these distributions on other key aspects such as data retention, switching pulse widths and endurance. **