A Low Power Magneto Resistive Random Access Memory Sense Amplifier Design using 45nm Technology

Abstract

The extensive development of CMOS circuit to the nanometer technology faces various issues such as increased leakage current and higher power dissipation in the memory cell according to the increased transistor size. As an alternative memory technology, MRAM (Magnetoresistive Random Access Memory) technology is interpreted as a reliable universal memory as it has maximum data retention and robust endurance. In the beginning, the MRAM overcome the problems associated with the half select bits by utilizing the toggle mode writing of the Synthetic AntiFerromagnet (SAF) free layer. Further, the inception of Spin Transfer Torque (STT) has extended the growth of spintronic architecture with perpendicular Magnetic Tunnel Junctions (MJTs). In this research work, MRAM - Sense Amplifier (MRAM-SA) circuit is designed to improve the read and write operation. MRAM is designed with the help of IOT which helps to improve the area performances. The performance of the MRAM-SA circuit is analyzed using area, power, delay and current.