Abstract
An optimized process design of the p-type lateral extended drain MOS transistor (pLED-MOS) for PDP driver ICs is developed. The following issues such as surface damage, parasitic BJT punch-through phenomenon, impurity segregation effect and creep behavior of the breakdown voltage are investigated. Various approaches are therefore sought in order to solve these reliability problems by optimizing the process and device architecture. The methods have been verified by the TCAD simulation and experimental results.
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