Reliability of Multi-Layer Wiring Board Embedded with Two Dies in Stacked Configuration

Abstract

As electronic devices decrease in size and increase in functionality, their surface-mount components grow in number. This trend created a need for securing appropriate space in and on a wiring board to accommodate necessary components. Conventionally, dies are mounted on a wiring board. Much effort is spent for space savings. We have come up with a structure to include dies inside a wiring board and succeeded in fabricating the board in which two dies are embedded in a 3D stacked configuration. This new structure shrinks the foot print size and thus contributes to higher density and functionality of a semiconductor package and SiP. In addition, since the base material is polyimide, this board is as thin as 0.45 mm with two WLP (Wafer Level Package) dies (3 mm x 3 mm x 0.085 mm) embedded between any of 9 wiring layers. The module level warpage on the both sides of this board is 0.035 mm, so it is possible to mount components on the both sides. This board was fabricated based on our WABE technologyTM (Wafer and Board level Embedding technology) that includes a single step co-laminating process and embedded technology using conductive-paste-filled vias for establishing z-axis interlayer electrical connections. The conductive paste formed intermetallic compound with the copper foil and the via showed stable electrical connections by metallic bonding. Copper pads were fabricated on the dies by a wafer level process in advance. The polyimide-based films were laminated with adhesive and the dies were embedded. At the same time, electrical connections were established. This method enables the production of an embedded board by one-time curing after the alignment and fixing of necessary layers. We applied this method to the new structure that includes two dies in a 3D configuration to achieve a simple fabrication process using the single step co-lamination process. We evaluated the reliability of this board as below. The electric resistance was measured after various reliability tests including Temperature Cycle Test, Temperature Humidity Bias Test and Highly Accelerated Stress Test following a moisture sensitive reflow test (based on IPC/JEDEC J-STD-020 Level 3). From the results, there were no major defects observed in the test boards, either visually or functionally. This two-die embedding technology helps to realize the miniaturization and contribute to higher functionality of semiconductor packages and SiPs.