Reliability of Fan-Out Wafer-Level Packaging with Large Chips and Multiple Re-Distributed Layers

Abstract

In this study, the reliability (thermal-cycling and shock) performances of chip-first and die face-up FOWLP (fan-out wafer-level packaging) with a very large silicon chip (10mmx10mm) embedded in an epoxy molding compound (EMC) package (13.42mmx13.42mm) with three RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level package is assembled on a printed circuit board (PCB) with 908 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a 6-layer PCB. The sample sizes for the thermal-cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal-cycling test and shock test of the fan-out wafer-level package solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are constructed and analyzed for the fan-out package during thermal-cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the FOWLP solder joints and RDLs under thermal and shock conditions are provided.