Abstract

In this study, the warpages of a chip-first and die face-up FOWLP (fan-out wafer-level packaging) with a very large silicon chip (10mm×10mm×0.15mm) and three RDLs (redistributed layers) are measured and characterized. Emphasis is placed on the measurement and 3D finite element simulation of the warpages during the FOWLP fabrication processes, especially for: (a) right after PMC (post mold cure), (b) right after backgrinding of the EMC (epoxy molding compound) to expose the Cu-contact pads, and (c) the individual package (right after the solder ball mounting and dicing) vs. SMT (surface mount technology) reflow temperatures. The simulation results are compared to the measurement results. Some recommendations on controlling the warpages are provided.

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