Reliability characterization and activity analysis of lowRISC internal modules against single event upsets using fault injection and RTL simulation

Abstract

One of the concerns about satellites with sensitive electronic devices is the harmful radiation that produces effects like Single Event Upsets (SEUs), which can cause errors. SRAM-based FPGAs are extensively used to implement a wide range of digital circuits among which are soft processors. In this paper, we focus on two different issues: 1) characterizing the different modules of lowRISC to determine their sensitivity to errors in the FPGA configuration memory and 2) analyzing the activity level of the mentioned modules using RTL simulation to correlate the activity level and the sensitivity of the different modules of the soft processor. Fault injection campaigns have been performed in order to evaluate the reliability of these different modules. Experimental results show that the instruction cache module is the most sensitive module of lowRISC for the benchmarks considered. Therefore, this cache module could be protected using different protection techniques to increase the reliability of the microprocessor.