Reliability challenges of high performance PD SOI CMOS with ultra-thin gate dielectrics

Abstract

With the introduction of ultra-thin (<15Å) gate dielectrics, which have significantly higher nitrogen concentration, and thus a higher dielectric constant, many new reliability challenges need to be addressed. At the same time, high-performance transistors are now migrating from bulk to silicon-on-insulator (SOI) to boost the performance. This paper will discuss major reliability issues such as negative bias temperature instability (NBTI), hot carrier injection (HCI), time dependent dielectric breakdown (TDDB) and electro-static discharge stress (ESD), etc., facing the state of art technology for SOI.