Reliability Assessment of the Embedded DRAM Technology with PMOSFET Transfer Transistor and High-K Dielectrics (Ta2O5) MIM Capacitor

Abstract

In this paper, wafer level and product level reliability characteristics of embedded DRAM technology with high-K dielectric Ta <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> MIM capacitors have been analyzed. It is found although hot carrier injection can induce more apparent gate-induced-drain-leakage (GIDL) current than off-state bias temperature (BT) stress docs, BT stress still dominate the failure bit count increase in real circuit operation. In addition, it is also found the competition between gate-induced-drain-leakage (GIDL) current and the MIM dielectric leakage dominate the failure bit count (FBC) evolution behavior after reliability stress. With transistor doping profile optimization, a new phenomenon of FBC reduction with burn-in time can be observed, and it is attributed to the leakage reduction of MIM capacitor with high-K dielectric Ta <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> after stress