Abstract
The number of open defects in vias has increased with the introduction of the copper process, smaller geometries, and via counts in the order of billions for modern integrated circuits. The authors investigate reliability risks by estimating the Median Time to Failure (MTF) as a function of the void size in vias placed. The number of open defects in vias has increased with the introduction of the copper process, smaller geometries, and via counts in the order of billions for modern integrated circuits. The authors investigate reliability risks by estimating the Median Time to Failure (MTF) as a function of the void size in vias placed on signal paths.
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