Reliability Analysis of P+ Pickup on Anti-ESD Performance in Four CMOS Low-Voltage Technology Nodes

Abstract

ABSTRACTN-channel metal-oxide semiconductor field-effect transistor (MOSFET) devices in I/O ESD protection circuits are often drawn in the parallel multi-finger construction. However, a non-uniform turned-on characteristic always occurs with this type of construction; i.e. the resulting sub-MOSFETs cannot be turned on at the same time. The ESD high-current will thus be conducted through a few turned-on MOSFETs, seriously impacting the ESD reliability and capability. On the source-side, the P+ pickup layout placement influence on an nMOSFET ESD capability of input/output pads for power-management popular 0.6- to 0.18-μm BCD (bipolar–complementary metal oxide semiconductor–diffusion metal oxide semiconductor) CMOS (complementary metal oxide semiconductor) technologies is investigated in this paper. However, the It2 decreasing percentage in an even- and full-adding type of P+ pickup stripe in the source end, as compared with that of a corresponding NonePickup Ref. type, is actually disadvantageous to the ESD immunity. The secondary breakdown current (It2) decreasing percentages have a range of 2.43%–63.31% for the four process nodes. This is very serious for the three technology nodes especially in the ultra-deep submicron 0.18-μm technology. On the contrary, the 0.35-μm technology is a critical process node. Furthermore, the figure of merit (FOM) for a device's ESD performance in a multi-finger type MOSFET can be used to well characterize and predict the device's It2 behaviour using an empirical methodology proposed in this work.