Abstract
Spin-transfer torque magnetic random-access memory (STT-MRAM) is considered as a premiere candidate for replacing conventional six-transistors static random-access memory (6T-SRAM) in processor caches. This paper explores STT-MRAMs based on double-barrier magnetic tunnel junction with two reference layers (DMTJ), while operating at cryogenic temperatures (77 K). To deal with large dynamc energy and long latency of write operation, we suggest to significantly relax the non-volatility requirement of DMTJ devices at room temperature by reducing the cross-section area, while maintaining the typical 10-years retention time at the target operating temperature. This leads the cryogenic DMTJ-based STT-MRAM to be more energy-efficient than its 6T-SRAM counterpart under both read and write operations, while exhibiting smaller area footprint.
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