Relaxing device requirements for non-linearity in Deep Neural Networks accelerators with Phase Change Memory

Abstract

Analog circuits using non-volatile memory, such as Phase Change Memory (PCM), are expected as high-speed and low-power Deep Neural Networks (DNN) accelerators. This paper analyzes the relationship between the non-linearity of the non-volatile memory (NVM) and the number of Open Loop Turnings (OLT) executed before Closed Loop Turning (CLT). The non-linearity of the NVM is determined by the initial step ΔG0. For OLT = 50, the recognition rate of 0.975 is achieved for ΔG0 = 8%. The analysis present that we achieve the same recognition rate as software even with highly non-linear NVM by inserting CLT before saturated NVM affects recognition accuracy.