Abstract
This paper introduces an energy-efficient design method for Deep Neural Network (DNN) accelerator. Although GPU is widely used for DNN acceleration, its huge power consumption limits practical usage on mobile devices. Recent DNN accelerators are dedicated to high energy-efficiency to realize real-time DNN acceleration with low power consumption. But a hardware-oriented algorithm is essential for realistic implementation. Therefore, various techniques of network compression are applied with the DNN accelerators that utilize several schemes to reduce computational complexity in trade of accuracy loss. This work studies the optimization schemes and presents a DNN accelerator architecture by hardware-software co-optimization.
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