Relatively Low-k Ferroelectric Nonvolatile Memory Using Fast Ramping Fast Cooling Annealing Process

Abstract

Hafnia-based ferroelectric field-effect transistors (FeFETs) with low power, scalability, and nonvolatile switching can overcome the performance limitations of conventional von Neumann computing technology. However, achieving a large memory window and excellent endurance in FeFET devices composed of two capacitors, such as ferroelectric and interfacial insulator capacitors, remains a challenge due to the strong electric field applied to the insulator, which accounts for the low permittivity ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> ) of interfacial insulator. In addition, write disturb (WD) is considered to be a hurdle in the practical array operation of 1T-type FeFET devices. In this study, we propose a core process in which the dielectric constant and grain size of hafnia ferroelectric are adjusted by the ramping/cooling process, achieving high speed (20 ns), high reliability (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> ), and negligible disturb (0 V in 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3{V}_{dd}$ </tex-math></inline-formula> operation) FeFET. This results from effective voltage drop and switching across a relatively low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> ferroelectric capacitor that is connected with an interfacial insulator. Intriguingly, using low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> HfZrO as a gate, the proposed 3-D structure FeFET exhibits an improved memory window and robustness in WD in the array operation. These results suggest an informative way to design a high memory performance of FeFETs for future applications.