Abstract
The concept of the streamlined processor architecture with simplified instruction set — Reduced Instruction Set Computer — became very attractive during last years. Started by the Berkeley RISC [1], Stanford MIPS [2] and IBM Project 801 [6] the concept matured in the wide spectrum of the computer architectures. The paper presents some notes concerning RISC and the concept of a register array processor. The Simplified PRogram INTerpreter (SPRINT) is described file for both data and instruction sequences, two-modes register addressing and the context switching mechanism.
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