Abstract

Static RAM-based field programmable gate arrays (SRAM-based FPGAs) are widely adopted in trigger and data acquisition systems of high-energy physics detectors for implementing fast logic due to their reconfigurability, large real-time processing capabilities and embedded high-speed serial IOs. These devices are sensitive to radiation-induced upsets, which may alter the functionality of the implemented circuit. Presently, their usage on-detector is limited and there is a strong interest in finding solutions for improving their tolerance to radiation-induced upsets. In this paper, we show a novel configuration-redundancy generation and scrubbing technique for SRAM-based FPGAs. It leads to a power saving with respect to other solutions in the literature. Moreover, our technique is compatible with several Xilinx FPGA families. Our solution does not require neither the usage of external memories nor third-party layout tools. We describe an example of our solution applied to a benchmark design implemented in a Xilinx Kintex-7 FPGA. In order to prove the effectiveness of the solution, we present results from a proton irradiation test.

Highlights

  • S TATIC RAM-based field programmable gate arrays (SRAM-based Field programmable gate array (FPGA)) [1], [2] are widely adopted in trigger and data acquisition systems of high-energy physics (HEP)experiments for implementing fast logic due to their reconfigurability, large real-time processing capabilities and embedded high-speed serial IOs

  • We show a demonstrator of our solution applied to a benchmark design implemented in a Xilinx Kintex-7 FPGA, and we present results from irradiation tests performed at Laboratori Nazionali del Sud (Catania, Italy) with a 62-MeV proton beam

  • We developed a configuration IO library, written in Tool Command Language (Tcl), which permits to write and read individual frames via a joint test action group (JTAG) programming cable connected to the FPGA

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Summary

INTRODUCTION

S TATIC RAM-based field programmable gate arrays (SRAM-based FPGAs) [1], [2] are widely adopted in trigger and data acquisition systems of high-energy physics (HEP). Scrubbing techniques based on configuration redundancy have been developed in order to avoid external memories and correct MBUs at the same time It cannot be classified as a scrubber, the patent disclosed in [13] shows a very interesting FPGA architecture and design implementation flow aimed at generating redundant configuration at the bit level. The Rapidsmith tool is used for replicating the layout of a module three times, generating three identical subsets of the configuration, and the Authors of the cited work exploit modular redundancy to generate configuration redundancy In this implementation, the scrubbing logic and a voter for the three modules are implemented in the fabric.

PROPOSED SCRUBBING METHOD
Configuration-Redundancy Generation
Configuration Upsets Detection and Correction
Default-Value Frames
COMPARISON WITH OTHER FRAME-LEVEL SCRUBBING TECHNIQUES
TEST SETUP
BEAM TEST RESULTS
CONCLUSION
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