A Self-Repairing and Adaptive FPGA-based High-speed Serial Link

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High-speed serial links for trigger and data acquisition (TDAQ) systems in High Energy Physics (HEP) experiments are often implemented by means of Static RAM-based Field Programmable Gate Array (SRAM-based FPGAs). However, due to the sensitivity of SRAM-based FPGA to radiation-induced upsets, their usage is limited to off-detector electronics. In order to benefit of SRAM-based FPGAs reprogrammability and high performance in the data transmission, also in a harsh radiation environment, many techniques have been developed: memory configuration correction (memory scrubbing), hardware redundancy (e.g. Triple Modular Redundancy, TMR) and information redundancy (e.g. Forward Error Correcting Code, FEC).In this paper we describe the architecture of the bidirectional serial link running at 6.25 Gbps we implemented on the Xilinx Kintex-7 SRAM-FPGA devices. With the aim of using the link also in a radiation environment, we chose a robust error correction scheme for the line coding, we designed and incorporated a configuration scrubbing in the link architecture and we explored different TMR strategies.We present a link which offers several original features. It can repair itself thanks to the custom embedded scrubber we designed. It is also capable of self-adjusting its line code scheme depending on the measured error faults and transmitted errors. We show the effective Bit Error Ratio as a function of the measured induced upsets. Besides, we present the performance of the link in terms of mean time between failures (MTBF) and mean time between loss of lock.