Redundancy techniques for SRAM leakage reduction in presence of within-die delay variation

Abstract

Within-die variations are increasing with technology scaling, resulting in similarly designed SRAM cells show different delays at different parts of the same chip. We optimally choose higher threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) and/or gate-oxide thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> ) for SRAM transistors so as to reduce leakage; consequently, cells delay increases, but due to within-die variation, only some (not all) of them violate original timing of the SRAM array, and hence, we can compensate them by adding reduncancies. In this paper we present two types of redundancy: spare cache ways for caches, and spare rows/columns for general SRAM arrays.