Redundancy design of a wafer scale and high-speed FFT processor

Abstract

The purpose of this paper is to provide a realization of FFT processors capable of real time processing of image signals. All of the arithmetic operations in such FFT processors must be achieved with hardware technology, so that the chip size of the processor LSI is wafer scale. To realize such WSI processors, this paper introduces redundancy technology. A redundant system design is shown in which special emphasis is placed on the chip area of the interconnection lines between butterflies as follows: 1) In the design of the non-redundant FFT processor, the chip area of the interconnection lines is reduced as much as possible. 2) A redundant structure capable of recovering from defects in the interconnection lines is proposed. 3) A yield equation is derived in which the entire effect of interconnection area is considered. 4) In the redundant system design, the total redundant chip area, including the chip area for interconnection lines and multiplexing switches, is minimized. It is indicated that an FFT processor whose chip area is 120 times that of the standard LSI with 50% yield may be realized with a 6% increase in chip area but without decreasing the yield.