Reduction of DC-link Ripples for SiC-based Three-phase Four-wire Inverters with Unbalanced Loads

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Three-phase inverters are widely used in the smart grid to integrate renewable energy resources. When the inverters are used to feed the unbalanced three-phase loads, the three-phase four-wire inverters are usually required to provide the current path for neutral currents. However, unbalanced loads will cause undesirable second-order ripples on DC bus. Conventional three-phase four-wire inverters with neutral legs can not address this challenge. Bulky capacitors or extra active circuits are still required to reduce the ripples. This inevitably leads to increased size and cost of the system. Although SiC-based converters have the advantage of achieving high power density, the DC-bus capacitance can not be reduced by simply replacing Si IGBTs with SiC MOSFETs. In this paper, a new topology of SiC-based three-phase four-wire inverters is proposed to reduce the DC-bus ripples without adding any additional hardware components. With the reduction of DC-bus ripples, the DC-buscapacitance can be reduced to achieve high power density. The equivalent circuit is analyzed and the control strategy for the proposed topology is designed. The proposed topology is built in Matlab/Simulink and simulation results are presented to verify the proposed topology.