Abstract

Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

Highlights

  • While the digital blocks of an integrated circuit continue to shrink, analog one hardly shrinks at all [1]

  • The access to UTBB (Ultra-Thin Body and Box) transistor Back-Gates (BG) offers an extended control of the threshold voltages of the transistors, opening new opportunities to exciting performances. This new complementary structure is based on a pair of BG cross-coupled inverters offering a fully symmetrical operation of complementary signals and will offer two other advantages very important for ring oscillator realization

  • We introduce a novel cell based on the cross-coupled backgate of the UTBB transistors

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Summary

Introduction

While the digital blocks of an integrated circuit continue to shrink (i.e., following Moore’s Law), analog one hardly shrinks at all [1]. We have still proposed a new inverter topology to realize a voltage controlled ring oscillator (VCRO) using FDSOI technology [2]. The access to UTBB (Ultra-Thin Body and Box) transistor Back-Gates (BG) offers an extended control of the threshold voltages of the transistors, opening new opportunities to exciting performances This new complementary structure is based on a pair of BG cross-coupled inverters offering a fully symmetrical operation of complementary signals and will offer two other advantages very important for ring oscillator realization. To reduce these effects, we introduce a novel cell based on the cross-coupled backgate of the UTBB transistors.

Current Mirror
Test Chip and Measurement
VCRO Design and Measurement
Figure 15
Conclusion
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