Abstract
The test application time is reduced while preserving the test quality or the fault coverage for circuit testing. The goal is achieved by reducing the number of scan flip-flops required for a scan-based design, and the basic procedure is to look for groups of The s-independent inputs in a group have the property that, when these inputs are combined together to share a scan flip-flop, the originally detectable faults are still detectable under the new scan structure. Though the number of test vectors may slightly increase, this can be offset by the significant reduction in the scan test width. Thus, the goal of test time reduction for scan test can be accomplished. For circuits which have few s-independent inputs, bypass storage cells are added to increase the s-independencies among all inputs. Experiments have been performed on MCNC benchmarks and the results are good. Several benchmark circuits have shown more than 90% of test time reduction.
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