Reducing Soft Error Rate in Logic Circuits Through Approximate Logic Functions

Abstract

The ever-decreasing charge required to represent a logic HIGH state at a circuit node has resulted in increased vulnerability of advanced ICs to Single-Event Upsets. Design approaches that address this threat to reliable operation of ICs are needed. The approach presented here uses logical masking through approximate functions to reduce the single-event error rate of a given circuit. Results on benchmark circuits show the effectiveness of this approach for mitigating the threat of SEU's